FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing

نویسندگان

چکیده

The slowdown of Moore's law and the power wall necessitates a shift toward finely tunable precision (a.k.a. transprecision) computing to reduce energy footprint. Hence, we need circuits capable performing floating-point operations on wide range precisions with high proportionality. We present FPnew, highly configurable open-source transprecision unit (TP-FPU), supporting standard custom FP formats. To demonstrate flexibility efficiency FPnew in general-purpose processor architectures, extend RISC-V ISA half-precision, bfloat16, an 8-bit format, as well SIMD vectors multiformat operations. Integrated into 32-bit core, our TP-FPU can speedup execution mixed-precision applications by 1.67× respect FP32 baseline, while maintaining end-to-end reducing system 37%. also integrate 64-bit five formats scalars or 2, 4, 8-way vectors. For this measured silicon manufactured Globalfoundries 22FDX technology across voltage from 0.45 1.2 V. achieves leading-edge efficiencies between 178 Gflop/sW (on FP64) 2.95 Tflop/sW mini-floats), performance 3.2 25.3 Gflop/s.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Transprecision Floating-Point Platform for Ultra-Low Power Computing

In modern low-power embedded platforms, the execution of floating-point (FP) operations emerges as a major contributor to the energy consumption of compute-intensive applications with large dynamic range. Experimental evidence shows that 50% of the energy consumed by a core and its data memory is related to FP computations. The adoption of FP formats requiring a lower number of bits is an inter...

متن کامل

Improved Fused Floating Point Add-Subtract Unit Architecture

Floating purpose is that the most vital a part of several fashionable chip. The amalgamate floating-point add–subtract unit is helpful for digital signal process (DSP) applications like quick Fourier rework (FFT) and separate circular function rework (DCT) butterfly operations. IEEE 754 normal specifies the ways for binary and decimal floating purpose arithmetic unit. Moreover, single precisene...

متن کامل

An FPGA-based Floating Point Unit for Rounding Error Analysis

Detection of floating-point rounding errors normally requires run-time analysis in order to be effective and software-based tools are seldom used due to the extremely high computational demands. In this paper we present a field programmable gate array (FPGA) based floating-point coprocessor which supports standard IEEE-754 arithmetic, user selectable precision and Monte Carlo Arithmetic (MCA). ...

متن کامل

Optimizer for Floating-Point Unit Generator

Nowadays digital circuits become more and more complex, and keep requiring higher performance and lower cost. To design a digital circuit, such as a floating-point unit (FPU), usually needs to explore a huge design space to optimize speed, power and area. However, there exists a fundamental tradeoff between these three metrics, and usually people want to find the Pareto optimal configurations c...

متن کامل

A Floating-Point Unit for Arithmetic Operations

In this paper we present a design for a floating point unit partially compliant with the IEEE 754 floating point standard. The unit fully implements comparisons and partially implements floating-point addition and multiplication. It is fully parametrized and may be used with floating point numbers whose composite fields have widths of any desired length.

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEEE Transactions on Very Large Scale Integration Systems

سال: 2021

ISSN: ['1063-8210', '1557-9999']

DOI: https://doi.org/10.1109/tvlsi.2020.3044752